Il existe un outil appelé cpuidque l'on peut utiliser pour rechercher des informations beaucoup plus détaillées que celles généralement présentes dans lshwou /proc/cpuinfo. Sur mon système Fedora 19, j'ai pu installer le package avec la commande suivante:
$ sudo yum install cpuid
Une fois installé, cpuidest un trésor de détails sur ceux sous-jacents CPU.
Plusieurs versions
Il existe au moins 2 versions d'un outil appelé cpuid. Sur Debian / Ubuntu:
$ dpkg -p cpuid
Package: cpuid
Priority: optional
Section: admin
Installed-Size: 68
Maintainer: Ubuntu MOTU Developers <ubuntu-motu@lists.ubuntu.com>
Architecture: amd64
Version: 3.3-9
Depends: libc6 (>= 2.5-0ubuntu1)
Size: 11044
Description: Intel and AMD x86 CPUID display program
This program displays the vendor ID, the processor specific features,
the processor name string, different kinds of instruction set
extensions present, L1/L2 Cache information, and so on for the
processor on which it is running.
.
Homepage: http://www.ka9q.net/code/cpuid/
Original-Maintainer: Aurélien GÉRÔME <ag@roxor.cx>
Sur CentOS / Fedora / RHEL:
$ rpm -qi cpuid
Name : cpuid
Version : 20130610
Release : 1.fc19
Architecture: x86_64
Install Date: Wed 29 Jan 2014 09:48:17 PM EST
Group : System Environment/Base
Size : 253725
License : MIT
Signature : RSA/SHA256, Sun 16 Jun 2013 12:30:11 PM EDT, Key ID 07477e65fb4b18e6
Source RPM : cpuid-20130610-1.fc19.src.rpm
Build Date : Sun 16 Jun 2013 05:39:24 AM EDT
Build Host : buildvm-13.phx2.fedoraproject.org
Relocations : (not relocatable)
Packager : Fedora Project
Vendor : Fedora Project
URL : http://www.etallen.com/cpuid.html
Summary : Dumps information about the CPU(s)
Description :
cpuid dumps detailed information about x86 CPU(s) gathered from the CPUID
instruction, and also determines the exact model of CPU(s). It supports Intel,
AMD, and VIA CPUs, as well as older Transmeta, Cyrix, UMC, NexGen, and Rise
CPUs.
REMARQUE: La sortie ci-dessous se concentrera exclusivement sur l'implémentation de Todd Allencpuid , c'est-à-dire celle emballée par Fedora.
Exemple
La section supérieure est assez standard.
$ cpuid -1 | less
CPU:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
model = 0x5 (5)
stepping id = 0x5 (5)
extended family = 0x0 (0)
extended model = 0x2 (2)
(simple synth) = Intel Core i3 / i5 / i7 (Clarkdale K0) / Pentium U5000 Mobile / Pentium P4505 / U3405 / Celeron Mobile P4000 / U3000 (Arrandale K0), 32nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1 (1)
cpu count = 0x10 (16)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
Mais les sections inférieures sont beaucoup plus éclairantes.
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = true
thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = true
hyper-threading / multi-core supported = true
therm. monitor = true
IA64 = false
pending break event = true
Il vous montrera des détails sur votre structure de cache:
cache and TLB information (2):
0x5a: data TLB: 2M/4M pages, 4-way, 32 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x55: instruction TLB: 2M/4M pages, fully, 7 entries
0xdd: L3 cache: 3M, 12-way, 64 byte lines
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0x2c: L1 data cache: 32K, 8-way, 64 byte lines
0x21: L2 cache: 256K MLC, 8-way, 64 byte lines
0xca: L2 TLB: 4K, 4-way, 512 entries
0x09: L1 instruction cache: 32K, 4-way, 64-byte lines
Encore plus de détails sur le cache de votre CPU:
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
La liste continue.
Références